This invention relates to a shift register circuit and a shift register system.
Along with the recent trend of high speed processing and digital processing of data, it comes to be necessary to provide the data with an arbitrary amount of delay or synchronize the external clocks in data transfer or data output. Besides, since high speed processing is required in video signals, parallel processing of data is often required. In such cases, a circuit for processing data of plural bits with a simultaneous delay is needed.
The shift register hitherto used in such cases is first explained below.
FIG. 1 shows a circuit diagram of a shift register which has been generally used so far. In FIG. 1, numeral 101 denotes a clock signal wire; element 102 is an inverter for inverting the clock; element 103 is an inverted clock signal wire for transmitting the clock inverted by the inverter 102; element 104 is a driver for feeding input data; element 105 is an input data wire, and element 107 is a step number control signal generation circuit for generating a step number control signal by receiving an external signal. Numerals 111, 113, and 115 denote transfer gates having the clock signal wire 101 connected to the gate of a P-channel transistor, and the inverted clock signal wire 102 connected to the gate of an N-channel transistor; elements 112, 114, 116 are transfer gates having the inverted clock signal wire 102 connected to the gate of the P-channel transistor gate, and the clock signal wire 101 connected to the gate of the N-channel transistor; elements 121 to 126 are inverters; elements 141, 143, and 145 are transfer gates controlled by the step number control signal and are connected to the input data wire 105, transfer data wires 174, 178, and output data wire 190; elements 151, 153, and 155 are inverters for inverting the step number control signal; elements 161, 163, and 165 are step number control signal wires for transmitting the inverted control signals from the inverters 151, 153, 155, respectively; elements 162, 164, 166 are step number control signal wires for sending the step number control signal from the step number control signal generation circuit 107; elements 171 to 182 are transfer data wires for transferring data in the shift register; and elements 190 is an output data wire.
In thus composed shift register shown in FIG. 1, when transferring data in a shift register consisting of n steps, if it is necessary to deliver the data which has been delayed for m periods of the clock (n greater than m), an external signal is received, and a step number control signal is sent from the step number control signal generation circuit 107. For example, when delivering data which has been delayed for 1 period of the clock, the step number control signal wire 164 becomes an H level, and the step number control signal wire 163 becomes an L level through the inverter. As a result, the transfer gate 143 connected to the step number control signal wire 164 and inverted step number control signal wire 163 is opened, and the transfer data wire 174 and output data wire 190 are connected each other. Therefore, when the clock signal wire 101 is at an L level and the inverted clock signal wire 103 is at an H level, the transfer gate 111 is opened, and the data entering the shift register from the driver 104 through the input data wire 105 is sent into the transfer data wire 171, and the inverted signal of the input data is sent into the transfer data wire 172 through the inverter 121. Next, when the clock signal wire 101 is at an H level and the inverted clock signal wire 103 is at an L level, the transfer gate 112 is opened, and the inverted signal of the input data is sent into the transfer data wire 173, and the input data is sent into the transfer data wire 174 by way of the inverter 122, and then it is further sent into the output data wire 190 through the transfer gate 143. In this way, the input data is delivered through the transfer gate in the process of transfer which is turned on by the step number control signal.
In this composition, however, the input data is sent from the transfer gate 143 or 145 or 147 into the output data wire 190 through transfer data wires 174, 178, or 182. At this time, if the shift register is composed of plural steps, the capacity of the output data wire becomes large, and the delay time increases. In this composition, therefore, in order to increase the driving capacity of the transistor of the inverter in each transfer step of the shift register, it is necessary to increase the size of the transistor in the transfer step, and when integrated, the circuit area of the shift register becomes very large.
In particular, in the case of data parallel processing such as video signal processing, since shift registers in multiple steps are required, the increase of the circuit area and increase of current consumption were serious problems hitherto.
FIG. 2 is a block diagram of a data filter using a conventional shift register. This is reported by Ninomiya in "Transmission system "MUSE" of High-Vision television broadcasting using satellites," Nikkei Electronics, Nov. 2, 1987, No. 433, pp. 189-212. In FIG. 2, numeral 191 denotes a frame delay wire; element 192 is a MUSE data input terminal; elements 193 to 196 are delay wires for delays 1H data; element is a conventional shift register; element 198 is an interpolated data; element 199 is a vertical movement vector changeover switch, and 200 is a horizontal movement vector changeover switch.
The operation of thus composed system is explained below. The data enters from the MUSE input terminal 192, and a necessary number of 1H delay wires 193 to 196 are passed by the vertical motion vector changeover switch 199, and are delayed, and are entered into the shift register 197. The data entering the shift register 197. The data entering the shift register 197 is fed into the horizontal movement vector changeover switch 200, and arbitrary steps are passed, and are delivered from the output terminal 198.
In this composition, the transistor at each transfer step of the shift register 197 must deliver the output through the horizontal movement vector changeover switch 200, and the transistor size is forced to be larger, and the area of the integrated circuit of shift register 197 is increased. Furthermore, the power consumption of the system increases.